September 15, 2025
The GIST New chip design cuts AI energy use by enabling smarter FPGA processing 
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A new innovation from Cornell researchers lowers the energy use needed to power artificial intelligence—a step toward shrinking the carbon footprints of data centers and AI infrastructure.
As AI systems become increasingly powerful, they also become more power-hungry—raising urgent questions about sustainability. The research team, from Cornell Tech and Cornell Engineering, is tackling that challenge by rethinking the hardware that powers AI, aiming to make it faster, more efficient and less energy-intensive.
The researchers received a Best Paper Award for their findings, presented at the International Conference on Field-Programmable Logic and Applications (FPL 2025), held from Sept. 1 to 5 in Leiden, Netherlands. The paper is available on the arXiv preprint server.
Their work focuses on a type of computer chip called a Field-Programmable Gate Array (FPGA). These chips are prized for their flexibility: Unlike traditional chips, they can be reprogrammed for different tasks after manufacturing. This makes them especially useful in rapidly evolving fields such as AI, cloud computing and wireless communication.
"FPGAs are everywhere—from network cards and communication base stations to ultrasound machines, CAT scans, and even washing machines," said co-author Mohamed Abdelfattah, assistant professor at Cornell Tech. "AI is coming to all of these devices, and this architecture helps make that transition more efficient,"
Inside each FPGA chip are computing units called logic blocks. These blocks contain components that can handle different types of computing. Lookup Tables (LUTs) are components that can conduct a wide range of logical operations depending on what the chip needs to do. Adder chains are components that perform fast arithmetic operations such as adding numbers—essential for tasks like image recognition and natural language processing.
In conventional FPGA designs, these components are tightly linked, meaning the adder chains can only be accessed through the LUTs. This limits the chip's efficiency, especially for AI workloads that rely heavily on arithmetic operations.
The research team developed "Double Duty," a new chip architecture, to address this problem. The design allows LUTs and adder chains to work independently and simultaneously within the same logic block. In other words, the chip can now do more with the exact same processing resources.
This innovation is particularly impactful for deep neural networks, AI models that mimic the human brain's processing of information. These models are often "unrolled" onto FPGAs—laid out as fixed circuits for faster, more efficient processing.
"We focused on a mode where FPGAs are actually really good at AI acceleration," said Abdelfattah, who is also affiliated with Cornell Engineering. "By making a small architectural change, we make these unrolled neural networks much more efficient, playing to the strengths of FPGAs instead of treating them like generic processors."
In testing, the Double Duty design reduced the space needed for specific AI tasks by more than 20% and improved overall performance on a large suite of circuits by nearly 10%. That means fewer chips could be used to perform the same work, resulting in lower energy use.
The impact goes beyond AI. "This change benefits traditional industries too," said Xilai Dai, a doctoral student in electrical and computer engineering and one of the paper's lead authors. "It helps with chip verification, wireless communication and any application that uses arithmetic. You can fit larger programs into smaller chips, which improves efficiency across the board."
The work began as an undergraduate research project by Dai, who continued developing the idea into a full-scale study during his studies at Cornell. The paper's other lead co-author, Junius Pun, a former research intern at Cornell Tech and a recent graduate of Nanyang Technological University, also played a key role in the architecture and modeling work.
The project also included researchers at the University of Toronto and the University of Waterloo, as well as engineers at Altera (formerly part of Intel).
"It was a great collaboration between academic partners and industry, with many moving pieces," Abdelfattah said. "It's a step toward using FPGAs in a way that plays to their strengths, making them truly efficient computing devices."
More information: Junius Pun et al, Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage, arXiv (2025). DOI: 10.48550/arxiv.2507.11709
Journal information: arXiv Provided by Cornell University Citation: New chip design cuts AI energy use by enabling smarter FPGA processing (2025, September 15) retrieved 16 September 2025 from https://techxplore.com/news/2025-09-ai-hardware-reimagined-energy.html This document is subject to copyright. Apart from any fair dealing for the purpose of private study or research, no part may be reproduced without the written permission. The content is provided for information purposes only.
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